Design and Architecture for Signal and Image Processing
Design and Architecture for Signal and Image Processing
18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025, Proceedings
Kamaleldin, Ahmed; Lorandel, Jordane
Springer International Publishing AG
04/2025
125
Mole
Inglês
9783031878961
Pré-lançamento - envio 15 a 20 dias após a sua edição
.- CSD-Driven Speedup in RISC-V Processor.
.- Efficient FPGA implementation of ViT Non-Linear Functions.
.- LiFT: Lightweight,FPGA-tailored 3D object detection based on LIDAR data.
.- Efficient Processing using AI for Image, Vision and Signal Applications.
.- A practical HW-Aware NAS flow for AI vision applications on embedded heterogeneous SoCs.
.- Endoscopy image classification for wireless cpasules with CNNs on microcontroller-based platforms.
.- Joint Underwater Depth Estimation and Dehazing from Single Image using Attention U-Net.
.- KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition.
.- Analysis of Emerging Techniques for Signal Processing Applications.
.- Novel scheduling and shifter networks for 5G LDPC decoders.
.- Comparison Between In-core Hardware IDS, Off-core Hardware IDS and Software IDS.
.- Comparative Study of Memory Optimization Techniques for Dataflow-modeled Applications.
.- CSD-Driven Speedup in RISC-V Processor.
.- Efficient FPGA implementation of ViT Non-Linear Functions.
.- LiFT: Lightweight,FPGA-tailored 3D object detection based on LIDAR data.
.- Efficient Processing using AI for Image, Vision and Signal Applications.
.- A practical HW-Aware NAS flow for AI vision applications on embedded heterogeneous SoCs.
.- Endoscopy image classification for wireless cpasules with CNNs on microcontroller-based platforms.
.- Joint Underwater Depth Estimation and Dehazing from Single Image using Attention U-Net.
.- KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition.
.- Analysis of Emerging Techniques for Signal Processing Applications.
.- Novel scheduling and shifter networks for 5G LDPC decoders.
.- Comparison Between In-core Hardware IDS, Off-core Hardware IDS and Software IDS.
.- Comparative Study of Memory Optimization Techniques for Dataflow-modeled Applications.