Constructive Side-Channel Analysis and Secure Design
portes grátis
Constructive Side-Channel Analysis and Secure Design
15th International Workshop, COSADE 2024, Gardanne, France, April 9-10, 2024, Proceedings
Homma, Naofumi; Wacquez, Romain
Springer International Publishing AG
04/2024
282
Mole
9783031575426
15 a 20 dias
Descrição não disponível.
?Analyses and Tools.- Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.- On-chip evaluation of voltage drops and fault occurrence induced by Si backside EM injection.- EFFLUX-F2: A high performance hardware security evaluation board.- Attack Methods.- Practical Improvements to Statistical Ineffective Fault Attacks.- CAPABARA: A Combined Attack on CAPA.- Deep-Learning-Based Side-Channel Attacks.- Exploring Multi-Task Learning in the Context of Masked AES Implementations.- The Need for MORE: Unsupervised Side-channel Analysis with Single Network Training and Multi-output Regression.- Towards Private Deep Learning-Based Side-Channel Analysis using Homomorphic Encryption.- PUF/RNG.- Leakage Sources of the ICLooPUF: Analysis of a Side-Channel Protected Oscillator-Based PUF.- Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.- Lightweight Leakage-Resilient PRNG from TBCs using Superposition.- Cryptographic Implementations.- The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+.- HaMAYO: A Fault-Tolerant Reconfigurable Hardware Implementation of the MAYO Signature Scheme.- Combining Loop Shuffling and Code Polymorphism for Enhanced AES Side-Channel Security.
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artificial intelligence;authentication;computer hardware;computer networks;computer science;computer crime;authentication;computer security;computer systems;cryptography;data security;embedded systems;engineering;internet;software engineering;software design;smart cards;side channel attack;programming languages;network security
?Analyses and Tools.- Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.- On-chip evaluation of voltage drops and fault occurrence induced by Si backside EM injection.- EFFLUX-F2: A high performance hardware security evaluation board.- Attack Methods.- Practical Improvements to Statistical Ineffective Fault Attacks.- CAPABARA: A Combined Attack on CAPA.- Deep-Learning-Based Side-Channel Attacks.- Exploring Multi-Task Learning in the Context of Masked AES Implementations.- The Need for MORE: Unsupervised Side-channel Analysis with Single Network Training and Multi-output Regression.- Towards Private Deep Learning-Based Side-Channel Analysis using Homomorphic Encryption.- PUF/RNG.- Leakage Sources of the ICLooPUF: Analysis of a Side-Channel Protected Oscillator-Based PUF.- Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.- Lightweight Leakage-Resilient PRNG from TBCs using Superposition.- Cryptographic Implementations.- The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+.- HaMAYO: A Fault-Tolerant Reconfigurable Hardware Implementation of the MAYO Signature Scheme.- Combining Loop Shuffling and Code Polymorphism for Enhanced AES Side-Channel Security.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
artificial intelligence;authentication;computer hardware;computer networks;computer science;computer crime;authentication;computer security;computer systems;cryptography;data security;embedded systems;engineering;internet;software engineering;software design;smart cards;side channel attack;programming languages;network security
